Generates complete, simulatable analog circuits in milliseconds, outperforming search-based methods by over 600x.
April 1, 2026
Original Paper
ARCS: Autoregressive Circuit Synthesis with Topology-Aware Graph Attention and Spec Conditioning
arXiv · 2603.29068
The Takeaway
By combining graph VAEs with a novel RL method (GRPO) that handles cross-topology reward mismatches, it bypasses the need for thousands of slow SPICE simulations. This enables real-time design space exploration for hardware engineers that previously took hours or days.
From the abstract
I present ARCS, a system for amortized analog circuit generation that produces complete, SPICE-simulatable designs (topology and component values) in milliseconds rather than the minutes required by search-based methods. A hybrid pipeline combining two learned generators (a graph VAE and a flow-matching model) with SPICE-based ranking achieves 99.9% simulation validity (reward 6.43/8.0) across 32 topologies using only 8 SPICE evaluations, 40x fewer than genetic algorithms. For single-model infer